|Lattice LatticeECP3 HDR－60视频照相机开发方案|
|作者：Lattice 文章来源：Lattice 点击数： 更新时间：2015-3-12|
The LatticeECP3™ (EConomy Plus Third generation) family of FPGA devices is optimized to deliver high performance features such as an enhanced DSP architecture, high speed SERDES and high speed source synchronous interfaces in an economical FPGA fabric. This combination is achieved through advances in device architecture and the use of 65nm technology making the devices suitable for high-volume, high-speed, low-cost applications.
The LatticeECP3 device family expands look-up-table (LUT) capacity to 149K logic elements and supports up to 586 user I/Os. The LatticeECP3 device family also offers up to 320 18x18 multipliers and a wide range of parallel I/O standards. The LatticeECP3 FPGA fabric is optimized with high performance and low cost in mind. The LatticeECP3 devices utilize reconfigurable SRAM logic technology and provide popular building blocks such as LUT-based logic, distrib-uted and embedded memory, Phase Locked Loops (PLLs), Delay Locked Loops (DLLs), pre-engineered source synchronous I/O support, enhanced sysDSP slices and advanced configuration support, including encryption and dual-boot capabilities. The pre-engineered source synchronous logic implemented in the LatticeECP3 device family supports a broad range of interface standards, including DDR3, XGMII and 7:1 LVDS. The LatticeECP3 device family also features high speed SERDES with dedicated PCS functions. High jitter toler-ance and low transmit jitter allow the SERDES plus PCS blocks to be configured to support an array of popular data protocols including PCI Express, SMPTE, Ethernet (XAUI, GbE, and SGMII) and CPRI. Transmit Pre-empha-sis and Receive Equalization settings make the SERDES suitable for transmission and reception over various forms of media.
The LatticeECP3 devices also provide flexible, reliable and secure configuration options, such as dual-boot capa-bility, bit-stream encryption, and TransFR field upgrade features. The Lattice Diamond™ and ispLEVER® design software allows large complex designs to be efficiently imple-mented using the LatticeECP3 FPGA family. Synthesis library support for LatticeECP3 is available for popular logic synthesis tools. Diamond and ispLEVER tools use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeECP3 device. The tools extract the timing from the routing and back-annotate it into the design for timing verification. Lattice provides many pre-engineered IP (Intellectual Property) modules for the LatticeECP3 family. By using these configurable soft core IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity.
Each LatticeECP3 device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM™ Embedded Block RAM (EBR) and rows of sys- DSP™ Digital Signal Processing slices, as shown in Figure 2-1. The LatticeECP3-150 has four rows of DSP slices; all other LatticeECP3 devices have two rows of DSP slices. In addition, the LatticeECP3 family contains SERDES Quads on the bottom of the device. There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional Unit without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM and ROM functions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a twodimensional array. Only one type of block is used per row.
The LatticeECP3 devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large, dedicated 18Kbit fast memory blocks. Each sysMEM block can be configured in a variety of depths and widths as RAM or ROM. In addition, LatticeECP3 devices contain up to two rows of DSP slices. Each DSP slice has multipliers and adder/accumulators, which are the building blocks for complex signal processing capabilities. The LatticeECP3 devices feature up to 16 embedded 3.2Gbps SERDES (Serializer / Deserializer) channels. Each SERDES channel contains independent 8b/10b encoding / decoding, polarity adjust and elastic buffer logic. Each group of four SERDES channels, along with its Physical Coding Sub-layer (PCS) block, creates a quad. The functionality of the SERDES/PCS quads can be controlled by memory cells set during device configuration or by registers that are addressable during device operation. The registers in every quad can be programmed via the SERDES Client Interface (SCI). These quads (up to four) are located at the bottom of the devices. Each PIC block encompasses two PIOs (PIO pairs) with their respective sysI/O buffers. The sysI/O buffers of the LatticeECP3 devices are arranged in seven banks, allowing the implementation of a wide variety of I/O standards. In addition, a separate I/O bank is provided for the programming interfaces. 50% of the PIO pairs on the left and right edges of the device can be configured as LVDS transmit/receive pairs.
The PIC logic also includes pre-engineered support to aid in the implementation of high speed source synchronous standards such as XGMII, 7:1 LVDS, along with memory interfaces including DDR3. The LatticeECP3 registers in PFU and sysI/O can be configured to be SET or RESET. After power up and the device is configured, it enters into user mode with these registers SET/RESET according to the configuration setting, allowing the device entering to a known state for predictable system function. Other blocks provided include PLLs, DLLs and configuration functions. The LatticeECP3 architecture provides two Delay Locked Loops (DLLs) and up to ten Phase Locked Loops (PLLs). The PLL and DLL blocks are located at the end of the EBR/DSP rows. The configuration block that supports features such as configuration bit-stream decryption, transparent updates and dual-boot support is located toward the center of this EBR row. Every device in the LatticeECP3 family supports a sysCONFIG™ port located in the corner between banks one and two, which allows for serial or parallel device configuration. In addition, every device in the family has a JTAG port. This family also provides an on-chip oscillator and soft error detect capability. The LatticeECP3 devices use 1.2V as their core voltage.
LatticeECP3 FPGAs utilize Lattice’s third generation of cost optimized transceivers and a low-power 65-nm process FPGA architecture. Building on the successful LatticeECP2M™ FPGA family, LatticeECP3 devices deliver high-performance SERDES blocks, cascadable high-performance sysDSP™, ultra-high logic and sysMEM™ embedded RAM, distributed memory, sysCLOCK PLLs, DDR3 memory interface, and sysIO buffers. LatticeECP3 provides a low-cost, low-power programmable solution for a wide variety of wireless and wireline applications.
Higher Logic Density for Increased System Integration
• 17K to 149K LUTs
• 116 to 586 I/Os
• 150 Mbps to 3.2 Gbps for Generic 8b10b, 10-bit SERDES, and 8-bit SERDES modes
• Data Rates 230 Mbps to 3.2 Gbps per channel for all other protocols
• Up to 16 channels per device: PCI Express, SONET/SDH, Ethernet (1GbE, SGMII, XAUI), CPRI, SMPTE 3G and Serial RapidIO
• Fully cascadable slice architecture
• 12 to 160 slices for high performance multiply and accumulate
• Powerful 54-bit ALU operations
• Time Division Multiplexing MAC Sharing
• Rounding and truncation
• Each slice supports
Flexible Memory Resources
• Up to 6.85Mbits sysMEM™ Embedded Block RAM (EBR)
• 36K to 303K bits distributed RAM
sysCLOCK Analog PLLs and DLLs
• Two DLLs and up to ten PLLs per device
Pre-Engineered Source Synchronous I/O
• DDR registers in I/O cells
• Dedicated read/write levelling functionality
• Dedicated gearing logic
• Source synchronous standards support
–ADC/DAC, 7:1 LVDS, XGMII
–High Speed ADC/DAC devices
• Dedicated DDR/DDR2/DDR3 memory with DQS support
• Optional Inter-Symbol Interference (ISI)
correction on outputs
Programmable sysI/O™ Buffer Supports Wide Range of Interfaces
• On-chip termination
• Optional equalization filter on inputs
• LVTTL and LVCMOS 33/25/18/15/12
• SSTL 33/25/18/15 I, II
• HSTL15 I and HSTL18 I, II
• PCI and Differential HSTL, SSTL
• LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS
Flexible Device Configuration
• Dedicated bank for configuration I/Os
• SPI boot flash interface
• Dual-boot images supported
• Slave SPI
• TransFR™ I/O for simple field updates
• Soft Error Detect embedded macro
System Level Support
• IEEE 1149.1 and IEEE 1532 compliant
• Reveal Logic Analyzer
• ORCAstra FPGA configuration utility
• On-chip oscillator for initialization & general use
• 1.2V core power supply
The HDR-60 Video Camera Development Kit is a fully production-ready High Dynamic Range (HDR) camera, designed to fit into commercially available camera housings. The hardware is intended to support full 1080p resolution at 60 frames per second in streaming mode through the FPGA, without the need for an external frame buffer.
The integrated IONOS Image Signal Processing (ISP) IP pipeline from Lattice partner Helion GmbH provides end-to-end ISP support from sensor to displayable image and incorporates sensor interfacing, defective pixel correction and 2D noise reduction, high-quality 5 x 5 DeBayer, Color Correction Matrix, Fast Auto Exposure, Auto White Balance, HDR, Gamma Correction and Overlay (both character and graphics). Lattice HDMI PHY IP enables output to HDMI/DVI monitors.
The HDR-60 Video Camera Development Kit provides the industry’s fastest Auto-Exposure, very high quality Auto White Balance and HDR greater than 120dB. On-board Broadcom Broadreach™ PHY enables support for Ethernet over coax up to a length of 700 meters. The hardware can support up to 16-megapixel sensors, can hold up to two sensors simultaneously and can be easily programmed via a standard low-cost USB cable.
The Kit consists of two boards, the long HDR-60 Base Board and the square Nanovesta Sensor Board mounted on top of the Base Board. The base board is populated with a LatticeECP3-70, while the sensor board is equipped with an Aptina 720p High Dynamic Range (HDR) sensor. The hardware, however, is designed to support full 1080p resolution at 60 frames per second.
The Kit incorporates a plug-n-play demo that runs right out of the box at 60fps when connected to a HDMI or DVI monitor. It is designed to jump-start the design efforts of camera manufacturer’s planning to take advantage of the high-performance and low-power digital signal processing capabilities of Lattice FPGAs, the demo bitstream, board schematics and Gerber files that are available and free of charge to all purchasers of the Kit.
While the Kit is populated with a LatticeECP3-70 in order to provide ample space for a camera manufacturer’s integration of their own IP, the entire IONOS HDR Image Signal Processing (ISP) pipeline is capable of fitting into a LatticeECP3-35 device. This, coupled with the fact that the ISP pipeline needs no external frame buffer as well as the low power consumption of the LatticeECP3 FPGA, means that HDR-60 based cameras are extremely low cost to build and operate.
FPGA-based Image Signal Processing
Fully production-ready HDR camera design
1080p capable at 60 frames per second
Supports up to 16 megapixel sensors
Supports up to two sensors simultaneously
Full 60fps in streaming mode, needs no external frame buffer
Fast auto exposure instantly adjusts to changing light
Greater than 120 dB High Dynamic Range (HDR) performance
Direct HDMI / DVI output from FPGA
Extremely low latency
Comprehensive image processing IP library
On-board Broadcom® BroadreachTM PHY enables IP over coax
On-board FTDI chip provides easy programming via low cost USB cable
Lattice ECP3 FPGA系列AMC评…
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