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您现在的位置: 61IC电子在线 >> TI专栏 >> TI C6000 DSP和ARM >> OMAP-L1x处理器 >> 正文
  [组图]OMAPL138的uPP通信(2)---FPGA篇           ★★★ 【字体:
OMAPL138的uPP通信(2)---FPGA篇
作者:xjf616    文章来源:xjf616    点击数:    更新时间:2013-10-24    

系统架构

 

本系统组成如下图,FPGA挨个读取24AD通道中的数据,然后通过UPP方式传送给OMAPL138中的DSP核,经过一系列运算,DSP核通过DSPLINK方式将数据送到ARM核。

 

FPGA数据读取、存储、传送、数据识别问题

因为OMAPL138需要识别传送上来的数据是对应哪个通道的。所以FPGA对数据必须做一些处理以便于OMAPL138对数据分门别类。

方法一:

FPGA中生成一个FIFO,挨个读取24AD通道中的数据按次序存放到FIFO中,FIFO中存放满预定大小的数据量时再上传给OMAPL138,这样OMAPL138就知道第一个数据是对应通道1的,第二个数据是对应通道2的。

优点:简单,容易实现

缺点:如果其中一个数据出错或者漏传,那后面的一大堆数据都会被错误归类。

方法二:

AD通道输出数据是16位,将其扩展为32位,高16位作为标志位。例如,如果第一个AD通道读出来的0xDE33,那扩展为32位时其数据为0x0001DE33OMAPL138通过其高16位辨别这个数据是哪个通道的。

优点:不再像方法一担心数据传错了,传错也不会危害到整体。

缺点:OMAPL138UPP通信时16位的数据线,原来是需要传送数据,现在还要传送标志数据,这样直接导致传输效率打5折。但是对于能够到达150MB/s吞吐量的UPP来说,就算传输只能达到50%,也是能满足我目前这个系统的。

读取AD

以下是读取ad的代码,状态机的状态比较多,比较麻烦。

  1. module ads_ddio (
  2.                         clk,
  3.                         rst,
  4.                         eoc,
  5.                         datain,
  6.                         dataout,
  7.                         f_ncs,
  8.                         f_nrd,
  9.                         fifo_wr,
  10.                         f_c1,
  11.                         f_c2,
  12.                         f_c3,
  13.                         f_c4,
  14.                         f_c5,
  15.                         f_c6
  16.                     );

  17.                 
  18. input             clk,rst;
  19. input[1:0]        eoc;
  20. input[15:0]     datain;
  21. output             f_c1, f_c2, f_c3, f_c4, f_c5, f_c6;
  22. output[1:0]      f_ncs;
  23. output[1:0]             f_nrd;
  24. output fifo_wr;
  25. output[31:0]     dataout;


  26. reg[7:0] counter;
  27. reg[31:0] data_reg;
  28. reg state;
  29. reg[1:0] eoc1;
  30. reg[5:0] cstate,nstate;
  31. reg[1:0] f_nrd_reg,f_ncs_reg;
  32. reg fifo_wr_reg;

  33. parameter     SET_COUNT          = 8'hff,

  34.                 SET_CSRD_C1UA = 8'd23,
  35.                 SET_DATA_C1UA = 8'd24,
  36.                 SET_CSRD_C1UB = 8'd26,
  37.                 SET_DATA_C1UB = 8'd27,
  38.                 SET_CSRD_C1UC = 8'd29,
  39.                 SET_DATA_C1UC = 8'd30,
  40.                 SET_CSRD_C1IA = 8'd32,
  41.                 SET_DATA_C1IA = 8'd33,
  42.                 SET_CSRD_C1IB = 8'd35,
  43.                 SET_DATA_C1IB = 8'd36,
  44.                 SET_CSRD_C1IC = 8'd38,
  45.                 SET_DATA_C1IC = 8'd39,    
  46.                 
  47.                 SET_CSRD_C2UA = 8'd41,
  48.                 SET_DATA_C2UA = 8'd42,
  49.                 SET_CSRD_C2UB = 8'd44,
  50.                 SET_DATA_C2UB = 8'd45,            
  51.                 SET_CSRD_C2UC = 8'd47,
  52.                 SET_DATA_C2UC = 8'd48,    
  53.                 SET_CSRD_C2IA = 8'd50,
  54.                 SET_DATA_C2IA = 8'd51,            
  55.                 SET_CSRD_C2IB = 8'd53,
  56.                 SET_DATA_C2IB = 8'd54,
  57.                 SET_CSRD_C2IC = 8'd56,
  58.                 SET_DATA_C2IC = 8'd57,
  59.                     
  60.                 SET_FIFO_DATA = 8'd60, //上个状态+3
  61.                 
  62.                 SET_IDLE          = 8'd62;
  63.                 
  64.                 
  65. parameter     IDLE                 = 6'd0,
  66.                 CSRDN_C1UA        = 6'd1,
  67.                 DATA_C1UA         = 6'd2,
  68.                 DATA1_C1UA = 6'd3,
  69.                 CSRDN_C1UB        = 6'd4,
  70.                 DATA_C1UB         = 6'd5,
  71.                 DATA1_C1UB = 6'd6,
  72.                 CSRDN_C1UC        = 6'd7,
  73.                 DATA_C1UC         = 6'd8,
  74.                 DATA1_C1UC = 6'd9,
  75.                 CSRDN_C1IA        = 6'd10,
  76.                 DATA_C1IA         = 6'd11,
  77.                 DATA1_C1IA = 6'd12,
  78.                 CSRDN_C1IB        = 6'd13,
  79.                 DATA_C1IB         = 6'd14,
  80.                 DATA1_C1IB = 6'd15,
  81.                 CSRDN_C1IC        = 6'd16,
  82.                 DATA_C1IC         = 6'd17,
  83.                 DATA1_C1IC = 6'd18,
  84.                 
  85.                 CSRDN_C2UA        = 6'd19,
  86.                 DATA_C2UA         = 6'd20,
  87.                 DATA1_C2UA = 6'd21,
  88.                 CSRDN_C2UB        = 6'd22,
  89.                 DATA_C2UB         = 6'd23,
  90.                 DATA1_C2UB = 5'd24,
  91.                 CSRDN_C2UC        = 6'd25,
  92.                 DATA_C2UC         = 6'd26,
  93.                 DATA1_C2UC = 6'd27,
  94.                 CSRDN_C2IA        = 6'd28,
  95.                 DATA_C2IA         = 6'd29,
  96.                 DATA1_C2IA = 6'd30,
  97.                 CSRDN_C2IB        = 6'd31,
  98.                 DATA_C2IB         = 6'd32,
  99.                 DATA1_C2IB = 6'd33,
  100.                 CSRDN_C2IC        = 6'd34,
  101.                 DATA_C2IC         = 6'd35,
  102.                 DATA1_C2IC = 6'd36,
  103.                 FIFO_DATA = 6'd37;                


  104. wire csrd_n_c1ua_req;
  105. wire csrd_n_c1ub_req;
  106. wire csrd_n_c1uc_req;
  107. wire csrd_n_c1ia_req;
  108. wire csrd_n_c1ib_req;
  109. wire csrd_n_c1ic_req;

  110. wire csrd_n_c2ua_req;
  111. wire csrd_n_c2ub_req;
  112. wire csrd_n_c2uc_req;
  113. wire csrd_n_c2ia_req;
  114. wire csrd_n_c2ib_req;
  115. wire csrd_n_c2ic_req;


  116. wire data_c1ua_req;
  117. wire data_c1ub_req;
  118. wire data_c1uc_req;
  119. wire data_c1ia_req;
  120. wire data_c1ib_req;
  121. wire data_c1ic_req;

  122. wire data_c2ua_req;
  123. wire data_c2ub_req;
  124. wire data_c2uc_req;
  125. wire data_c2ia_req;
  126. wire data_c2ib_req;
  127. wire data_c2ic_req;

  128. wire fifo_data_req;

  129. wire idle_req;

  130. assign f_c1 = 1'b1;
  131. assign f_c2 = 1'b0;
  132. assign f_c3 = 1'b1;
  133. assign f_c4 = 1'b0;
  134. assign f_c5 = 1'b0;
  135. assign f_c6 = 1'b0;

  136. assign dataout = data_reg;

  137. assign csrd_n_c1ua_req = (counter == SET_CSRD_C1UA);
  138. assign csrd_n_c1ub_req = (counter == SET_CSRD_C1UB);
  139. assign csrd_n_c1uc_req = (counter == SET_CSRD_C1UC);
  140. assign csrd_n_c1ia_req = (counter == SET_CSRD_C1IA);
  141. assign csrd_n_c1ib_req = (counter == SET_CSRD_C1IB);
  142. assign csrd_n_c1ic_req = (counter == SET_CSRD_C1IC);

  143. assign csrd_n_c2ua_req = (counter == SET_CSRD_C2UA);
  144. assign csrd_n_c2ub_req = (counter == SET_CSRD_C2UB);
  145. assign csrd_n_c2uc_req = (counter == SET_CSRD_C2UC);
  146. assign csrd_n_c2ia_req = (counter == SET_CSRD_C2IA);
  147. assign csrd_n_c2ib_req = (counter == SET_CSRD_C2IB);
  148. assign csrd_n_c2ic_req = (counter == SET_CSRD_C2IC);


  149. assign data_c1ua_req = (counter == SET_DATA_C1UA);
  150. assign data_c1ub_req = (counter == SET_DATA_C1UB);
  151. assign data_c1uc_req = (counter == SET_DATA_C1UC);
  152. assign data_c1ia_req = (counter == SET_DATA_C1IA);
  153. assign data_c1ib_req = (counter == SET_DATA_C1IB);
  154. assign data_c1ic_req = (counter == SET_DATA_C1IC);

  155. assign data_c2ua_req = (counter == SET_DATA_C2UA);
  156. assign data_c2ub_req = (counter == SET_DATA_C2UB);
  157. assign data_c2uc_req = (counter == SET_DATA_C2UC);
  158. assign data_c2ia_req = (counter == SET_DATA_C2IA);
  159. assign data_c2ib_req = (counter == SET_DATA_C2IB);
  160. assign data_c2ic_req = (counter == SET_DATA_C2IC);


  161. assign fifo_data_req = (counter == SET_FIFO_DATA);
  162. assign idle_req = (counter == SET_IDLE);
  163. assign f_nrd[0] = (cstate == DATA_C1UA || cstate == CSRDN_C1UA || cstate == DATA_C1UB || cstate == CSRDN_C1UB || cstate == DATA_C1UC || cstate == CSRDN_C1UC || cstate == DATA_C1IA || cstate == CSRDN_C1IA || cstate == DATA_C1IB || cstate == CSRDN_C1IB || cstate == DATA_C1IC || cstate == CSRDN_C1IC ) ? f_nrd_reg[0] : 1'b1;
  164. assign f_ncs[0] = (cstate == DATA_C1UA || cstate == CSRDN_C1UA || cstate == DATA_C1UB || cstate == CSRDN_C1UB || cstate == DATA_C1UC || cstate == CSRDN_C1UC || cstate == DATA_C1IA || cstate == CSRDN_C1IA || cstate == DATA_C1IB || cstate == CSRDN_C1IB || cstate == DATA_C1IC || cstate == CSRDN_C1IC ) ? f_ncs_reg[0] : 1'b1;
  165. assign f_nrd[1] = (cstate == DATA_C2UA || cstate == CSRDN_C2UA || cstate == DATA_C2UB || cstate == CSRDN_C2UB || cstate == DATA_C2UC || cstate == CSRDN_C2UC || cstate == DATA_C2IA || cstate == CSRDN_C2IA || cstate == DATA_C2IB || cstate == CSRDN_C2IB || cstate == DATA_C2IC || cstate == CSRDN_C2IC ) ? f_nrd_reg[1] : 1'b1;
  166. assign f_ncs[1] = (cstate == DATA_C2UA || cstate == CSRDN_C2UA || cstate == DATA_C2UB || cstate == CSRDN_C2UB || cstate == DATA_C2UC || cstate == CSRDN_C2UC || cstate == DATA_C2IA || cstate == CSRDN_C2IA || cstate == DATA_C2IB || cstate == CSRDN_C2IB || cstate == DATA_C2IC || cstate == CSRDN_C2IC ) ? f_ncs_reg[1] : 1'b1;
  167. assign fifo_wr = ( /* cstate ==DATA_C1UA ||*/ cstate == DATA_C1UB || cstate == DATA_C1UC || cstate == DATA_C1IA || cstate == DATA_C1IB || cstate == DATA_C1IC || cstate == DATA_C2UA || cstate == DATA_C2UB || cstate == DATA_C2UC || cstate == DATA_C2IA || cstate == DATA_C2IB || cstate == DATA_C2IC ||cstate == FIFO_DATA ) ? fifo_wr_reg : 1'b0;



  168. always @ (posedge clk or negedge rst)
  169.     if(!rst)
  170.         cstate <= IDLE;
  171.     else
  172.         cstate <= nstate;

  173. always @ (cstate or fifo_data_req or csrd_n_c1ua_req or data_c1ub_req or csrd_n_c1uc_req or data_c1ia_req or data_c1ib_req or data_c1ic_req or csrd_n_c2ua_req or data_c2ub_req or csrd_n_c2uc_req or data_c2ia_req or data_c2ib_req or data_c2ic_req)
  174.     case (cstate)
  175.         IDLE:
  176.             if(csrd_n_c1ua_req)
  177.                 nstate <= CSRDN_C1UA;
  178.             else
  179.                 nstate <= IDLE;
  180.          CSRDN_C1UA:
  181.             if(data_c1ua_req)
  182.                 nstate <= DATA_C1UA;
  183.             else
  184.                 nstate <= CSRDN_C1UA;
  185.          DATA_C1UA:
  186.             nstate <= DATA1_C1UA;
  187.          DATA1_C1UA:
  188.             if(csrd_n_c1ub_req)
  189.                 nstate <= CSRDN_C1UB;
  190.             else
  191.                 nstate <= DATA1_C1UA;
  192.          CSRDN_C1UB:
  193.             if(data_c1ub_req)
  194.                 nstate <= DATA_C1UB;
  195.             else
  196.                 nstate <= CSRDN_C1UB;
  197.          DATA_C1UB:
  198.             nstate <= DATA1_C1UB;
  199.          DATA1_C1UB:
  200.             if(csrd_n_c1uc_req)
  201.                 nstate <= CSRDN_C1UC;
  202.             else
  203.                 nstate <= DATA1_C1UB;        
  204.          CSRDN_C1UC:
  205.             if(data_c1uc_req)
  206.                 nstate <= DATA_C1UC;
  207.             else
  208.                 nstate <= CSRDN_C1UC;
  209.          DATA_C1UC:
  210.             nstate <= DATA1_C1UC;
  211.          DATA1_C1UC:
  212.             if(csrd_n_c1ia_req)
  213.                 nstate <= CSRDN_C1IA;
  214.             else
  215.                 nstate <= DATA1_C1UC;            
  216.          CSRDN_C1IA:
  217.             if(data_c1ia_req)
  218.                 nstate <= DATA_C1IA;
  219.             else
  220.                 nstate <= CSRDN_C1IA;
  221.          DATA_C1IA:
  222.             nstate <= DATA1_C1IA;
  223.          DATA1_C1IA:
  224.             if(csrd_n_c1ib_req)
  225.                 nstate <= CSRDN_C1IB;
  226.             else
  227.                 nstate <= DATA1_C1IA;        
  228.          CSRDN_C1IB:
  229.             if(data_c1ib_req)
  230.                 nstate <= DATA_C1IB;
  231.             else
  232.                 nstate <= CSRDN_C1IB;
  233.          DATA_C1IB:
  234.             nstate <= DATA1_C1IB;
  235.          DATA1_C1IB:
  236.             if(csrd_n_c1ic_req)
  237.                 nstate <= CSRDN_C1IC;
  238.             else
  239.                 nstate <= DATA1_C1IB;    
  240.          CSRDN_C1IC:
  241.             if(data_c1ic_req)
  242.                 nstate <= DATA_C1IC;
  243.             else
  244.                 nstate <= CSRDN_C1IC;
  245.          DATA_C1IC:
  246.             nstate <= DATA1_C1IC;
  247.          DATA1_C1IC:
  248.             if(csrd_n_c2ua_req)
  249.                 nstate <= CSRDN_C2UA;
  250.             else
  251.                 nstate <= DATA1_C1IC;                
  252. /////////////////////////////////////////////////////////////////
  253.          CSRDN_C2UA:
  254.             if(data_c2ua_req)
  255.                 nstate <= DATA_C2UA;
  256.             else
  257.                 nstate <= CSRDN_C2UA;
  258.          DATA_C2UA:
  259.             nstate <= DATA1_C2UA;
  260.          DATA1_C2UA:
  261.             if(csrd_n_c2ub_req)
  262.                 nstate <= CSRDN_C2UB;
  263.             else
  264.                 nstate <= DATA1_C2UA;
  265.          CSRDN_C2UB:
  266.             if(data_c2ub_req)
  267.                 nstate <= DATA_C2UB;
  268.             else
  269.                 nstate <= CSRDN_C2UB;
  270.          DATA_C2UB:
  271.             nstate <= DATA1_C2UB;
  272.          DATA1_C2UB:
  273.             if(csrd_n_c2uc_req)
  274.                 nstate <= CSRDN_C2UC;
  275.             else
  276.                 nstate <= DATA1_C2UB;        
  277.          CSRDN_C2UC:
  278.             if(data_c2uc_req)
  279.                 nstate <= DATA_C2UC;
  280.             else
  281.                 nstate <= CSRDN_C2UC;
  282.          DATA_C2UC:
  283.             nstate <= DATA1_C2UC;
  284.          DATA1_C2UC:
  285.             if(csrd_n_c2ia_req)
  286.                 nstate <= CSRDN_C2IA;
  287.             else
  288.                 nstate <= DATA1_C2UC;            
  289.          CSRDN_C2IA:
  290.             if(data_c2ia_req)
  291.                 nstate <= DATA_C2IA;
  292.             else
  293.                 nstate <= CSRDN_C2IA;
  294.          DATA_C2IA:
  295.             nstate <= DATA1_C2IA;
  296.          DATA1_C2IA:
  297.             if(csrd_n_c2ib_req)
  298.                 nstate <= CSRDN_C2IB;
  299.             else
  300.                 nstate <= DATA1_C2IA;        
  301.          CSRDN_C2IB:
  302.             if(data_c2ib_req)
  303.                 nstate <= DATA_C2IB;
  304.             else
  305.                 nstate <= CSRDN_C2IB;
  306.          DATA_C2IB:
  307.             nstate <= DATA1_C2IB;
  308.          DATA1_C2IB:
  309.             if(csrd_n_c2ic_req)
  310.                 nstate <= CSRDN_C2IC;
  311.             else
  312.                 nstate <= DATA1_C2IB;    
  313.          CSRDN_C2IC:
  314.             if(data_c2ic_req)
  315.                 nstate <= DATA_C2IC;
  316.             else
  317.                 nstate <= CSRDN_C2IC;
  318.          DATA_C2IC:
  319.             nstate <= DATA1_C2IC;
  320.          DATA1_C2IC:
  321.             if(fifo_data_req)
  322.                 nstate <= FIFO_DATA;
  323.             else
  324.                 nstate <= DATA1_C2IC;        
  325.          FIFO_DATA:
  326.             if(idle_req)
  327.                 nstate <= IDLE;
  328.             else
  329.                 nstate <= IDLE;
  330. /*            
  331.          DATA1_C1UB:
  332.             if(idle_req)
  333.                 nstate <= IDLE;
  334.             else
  335.                 nstate <= DATA1_C1UB;
  336. */
  337.          default:
  338.             nstate <= IDLE;
  339.     endcase

  340. always @ (posedge clk)
  341.     begin
  342.         case (cstate)
  343.             FIFO_DATA:
  344.                     fifo_wr_reg <= 1'b1; //把最后一个数据输出到fifo中详细请看signaltap2
  345.             DATA_C1UA:
  346.                 begin
  347.                     data_reg <= {16'h11,datain};
  348.                     f_nrd_reg[0] <= 1'b0;
  349.                     f_ncs_reg[0] <= 1'b0;
  350.     //                fifo_wr_reg <= 1'b1; //第一个数据刚好读到寄存器,还没放到fifo的总线上,所以第一个DATA状态不要拉高,详细请看signaltap2
  351.                 end
  352.             CSRDN_C1UA:
  353.                 begin
  354.                     f_nrd_reg[0] <= 1'b0;
  355.                     f_ncs_reg[0] <= 1'b0;
  356.                 end
  357.             DATA1_C1UA:
  358.                 begin
  359.                     f_nrd_reg[0] <= 1'b1;
  360.                     f_ncs_reg[0] <= 1'b1;
  361.                 end        
  362.             DATA_C1UB:
  363.                 begin
  364.                     data_reg <= {16'h12,datain};
  365.                     f_nrd_reg[0] <= 1'b0;
  366.                     f_ncs_reg[0] <= 1'b0;
  367.                     fifo_wr_reg <= 1'b1;
  368.                 end
  369.             CSRDN_C1UB:
  370.                 begin
  371.                     f_nrd_reg[0] <= 1'b0;
  372.                     f_ncs_reg[0] <= 1'b0;
  373.                 end
  374.             DATA1_C1UB:
  375.                 begin
  376.                     f_nrd_reg[0] <= 1'b1;
  377.                     f_ncs_reg[0] <= 1'b1;
  378.                 end        
  379.             DATA_C1UC:
  380.                 begin
  381.                     data_reg <= {16'h13,datain};
  382.                     f_nrd_reg[0] <= 1'b0;
  383.                     f_ncs_reg[0] <= 1'b0;
  384.                     fifo_wr_reg <= 1'b1;
  385.                 end
  386.             CSRDN_C1UC:
  387.                 begin
  388.                     f_nrd_reg[0] <= 1'b0;
  389.                     f_ncs_reg[0] <= 1'b0;
  390.                 end
  391.             DATA1_C1UC:
  392.                 begin
  393.                     f_nrd_reg[0] <= 1'b1;
  394.                     f_ncs_reg[0] <= 1'b1;
  395.                 end        
  396.             DATA_C1IA:
  397.                 begin
  398.                     data_reg <= {16'h14,datain};
  399.                     f_nrd_reg[0] <= 1'b0;
  400.                     f_ncs_reg[0] <= 1'b0;
  401.                     fifo_wr_reg <= 1'b1;
  402.                 end
  403.             CSRDN_C1IA:
  404.                 begin
  405.                     f_nrd_reg[0] <= 1'b0;
  406.                     f_ncs_reg[0] <= 1'b0;
  407.                 end
  408.             DATA1_C1IA:
  409.                 begin
  410.                     f_nrd_reg[0] <= 1'b1;
  411.                     f_ncs_reg[0] <= 1'b1;
  412.                 end    
  413.             DATA_C1IB:
  414.                 begin
  415.                     data_reg <= {16'h15,datain};
  416.                     f_nrd_reg[0] <= 1'b0;
  417.                     f_ncs_reg[0] <= 1'b0;
  418.                     fifo_wr_reg <= 1'b1;
  419.                 end
  420.             CSRDN_C1IB:
  421.                 begin
  422.                     f_nrd_reg[0] <= 1'b0;
  423.                     f_ncs_reg[0] <= 1'b0;
  424.                 end
  425.             DATA1_C1IB:
  426.                 begin
  427.                     f_nrd_reg[0] <= 1'b1;
  428.                     f_ncs_reg[0] <= 1'b1;
  429.                 end
  430.             DATA_C1IC:
  431.                 begin
  432.                     data_reg <= {16'h16,datain};
  433.                     f_nrd_reg[0] <= 1'b0;
  434.                     f_ncs_reg[0] <= 1'b0;
  435.                     fifo_wr_reg <= 1'b1;
  436.                 end
  437.             CSRDN_C1IC:
  438.                 begin
  439.                     f_nrd_reg[0] <= 1'b0;
  440.                     f_ncs_reg[0] <= 1'b0;
  441.                 end
  442.             DATA1_C1IC:
  443.                 begin
  444.                     f_nrd_reg[0] <= 1'b1;
  445.                     f_ncs_reg[0] <= 1'b1;
  446.                 end
  447. ///////////////////////////////////////
  448.             DATA_C2UA:
  449.                 begin
  450.                     data_reg <= {16'h21,datain};
  451.                     f_nrd_reg[1] <= 1'b0;
  452.                     f_ncs_reg[1] <= 1'b0;
  453.                     fifo_wr_reg <= 1'b1;
  454.                 end
  455.             CSRDN_C2UA:
  456.                 begin
  457.                     f_nrd_reg[1] <= 1'b0;
  458.                     f_ncs_reg[1] <= 1'b0;
  459.                 end
  460.             DATA1_C2UA:
  461.                 begin
  462.                     f_nrd_reg[1] <= 1'b1;
  463.                     f_ncs_reg[1] <= 1'b1;
  464.                 end        
  465.             DATA_C2UB:
  466.                 begin
  467.                     data_reg <= {16'h22,datain};
  468.                     f_nrd_reg[1] <= 1'b0;
  469.                     f_ncs_reg[1] <= 1'b0;
  470.                     fifo_wr_reg <= 1'b1;
  471.                 end
  472.             CSRDN_C2UB:
  473.                 begin
  474.                     f_nrd_reg[1] <= 1'b0;
  475.                     f_ncs_reg[1] <= 1'b0;
  476.                 end
  477.             DATA1_C2UB:
  478.                 begin
  479.                     f_nrd_reg[1] <= 1'b1;
  480.                     f_ncs_reg[1] <= 1'b1;
  481.                 end        
  482.             DATA_C2UC:
  483.                 begin
  484.                     data_reg <= {16'h23,datain};
  485.                     f_nrd_reg[1] <= 1'b0;
  486.                     f_ncs_reg[1] <= 1'b0;
  487.                     fifo_wr_reg <= 1'b1;
  488.                 end
  489.             CSRDN_C2UC:
  490.                 begin
  491.                     f_nrd_reg[1] <= 1'b0;
  492.                     f_ncs_reg[1] <= 1'b0;
  493.                 end
  494.             DATA1_C2UC:
  495.                 begin
  496.                     f_nrd_reg[1] <= 1'b1;
  497.                     f_ncs_reg[1] <= 1'b1;
  498.                 end        
  499.             DATA_C2IA:
  500.                 begin
  501.                     data_reg <= {16'h24,datain};
  502.                     f_nrd_reg[1] <= 1'b0;
  503.                     f_ncs_reg[1] <= 1'b0;
  504.                     fifo_wr_reg <= 1'b1;
  505.                 end
  506.             CSRDN_C2IA:
  507.                 begin
  508.                     f_nrd_reg[1] <= 1'b0;
  509.                     f_ncs_reg[1] <= 1'b0;
  510.                 end
  511.             DATA1_C2IA:
  512.                 begin
  513.                     f_nrd_reg[1] <= 1'b1;
  514.                     f_ncs_reg[1] <= 1'b1;
  515.                 end    
  516.             DATA_C2IB:
  517.                 begin
  518.                     data_reg <= {16'h25,datain};
  519.                     f_nrd_reg[1] <= 1'b0;
  520.                     f_ncs_reg[1] <= 1'b0;
  521.                     fifo_wr_reg <= 1'b1;
  522.                 end
  523.             CSRDN_C2IB:
  524.                 begin
  525.                     f_nrd_reg[1] <= 1'b0;
  526.                     f_ncs_reg[1] <= 1'b0;
  527.                 end
  528.             DATA1_C2IB:
  529.                 begin
  530.                     f_nrd_reg[1] <= 1'b1;
  531.                     f_ncs_reg[1] <= 1'b1;
  532.                 end
  533.             DATA_C2IC:
  534.                 begin
  535.                     data_reg <= {16'h26,datain};
  536.                     f_nrd_reg[1] <= 1'b0;
  537.                     f_ncs_reg[1] <= 1'b0;
  538.                     fifo_wr_reg <= 1'b1;
  539.                 end
  540.             CSRDN_C2IC:
  541.                 begin
  542.                     f_nrd_reg[1] <= 1'b0;
  543.                     f_ncs_reg[1] <= 1'b0;
  544.                 end
  545.             DATA1_C2IC:
  546.                 begin
  547.                     f_nrd_reg[1] <= 1'b1;
  548.                     f_ncs_reg[1] <= 1'b1;
  549.                 end
  550. ///////////////////////////////////////
  551.             IDLE:
  552.                 begin
  553.                     data_reg <= {16'h88,16'h00};
  554.                 //    fifo_wr_reg <= 1'b1;
  555.                 end
  556.         default: ;
  557.         endcase
  558.     end



  559. always @ (posedge clk)
  560.     if(!rst)
  561.         begin
  562.             counter <= 8'd0;
  563.             eoc1 <= 1'd0;
  564.             state <= 1'd0;
  565.         end
  566.     else
  567.         begin
  568.             eoc1      <= eoc;
  569.             case (state)
  570.                     1'd0:
  571.                             begin
  572.                                     counter <= 8'd0;
  573.                                     if(eoc & (~eoc1))
  574.                                             begin
  575.                                                     state     <=     1'd1;
  576.                                                     counter    <=        counter + 8'd1;
  577.                                             end
  578.                             end
  579.                     1'd1:
  580.                             begin
  581.                                     if(counter == SET_COUNT)
  582.                                             begin
  583.                                                     state     <=     1'd0;
  584.                                                     counter     <=     8'd0;
  585.                                             end
  586.                                     else
  587.                                             if(eoc & (~eoc1))
  588.                                                     begin
  589.                                                             counter <= 8'd0;
  590.                                                     end
  591.                                             else
  592.                                                     counter <=     counter + 8'd1;
  593.                             end
  594.                 endcase
  595.      end
  596. endmodule


FIFO传送判断条件



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  1. module fifo_switch(
  2.                         clk,
  3.                         rst,
  4.                         almost_full,
  5.                         empty,
  6.                         rdreq
  7.                    );
  8. input clk,rst;
  9. input almost_full,empty;
  10. output rdreq;

  11. reg state = 1'b0;

  12. reg almost_full_p, empty_p;


  13. assign rdreq = state ? 1'b1 : 1'b0;

  14. always @ (posedge clk)
  15.     if(!rst)
  16.         begin
  17.             almost_full_p <= 1'b0;
  18.             empty_p    <= 1'b0;
  19.         end
  20.     else
  21.         begin
  22.             almost_full_p <= almost_full;
  23.             empty_p <= empty;
  24.         end
  25.     
  26. always @ (posedge clk)
  27.     case (state)
  28.         1'b0:
  29.             if(almost_full & ~almost_full_p)
  30.                 state <= 1'b1;
  31.         1'b1:
  32.             if(empty & ~empty_p)
  33.                 state <= 1'b0;
  34.     endcase
  35.     
  36.     
  37. endmodule

UPP接口



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  1. module uPP_ddio(
  2.                     clk,
  3.                     oe,
  4.                     datain,
  5.                     dataout
  6.                     );
  7. input oe;
  8. input clk;
  9. input[31:0]     datain;
  10. output[15:0]     dataout;        
  11. reg[15:0]         data_reg;
  12. reg                 state         = 0;

  13. //assign



  14.    dataout = (oe == 1) ? data_reg : 16'd0 ;
  15. assign dataout = data_reg;
  16. always @ (posedge clk)
  17.     begin
  18.         state <= ~state;
  19.         if(state)
  20.             data_reg <= datain[31:16];
  21.         else
  22.             data_reg <= datain[15:0];
  23.     end
  24.     
  25. endmodule


最后整体图:

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