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您现在的位置: 61IC电子在线 >> TI专栏 >> TI C6000 >> TMS320C66x DSP >> 正文
  [组图]TI 66AK2Hx系统级芯片(SoC)开发方案           ★★★ 【字体:
TI 66AK2Hx系统级芯片(SoC)开发方案
作者:TI    文章来源:TI    点击数:    更新时间:2014-4-8    
TI公司的66AK2H14/12/06是多核DSP+ARM KeyStone II系统级芯片(SoC),集成了四个ARM® Cortex™-A15 MPCore™处理器和多达八个采用KeyStone II架构的TMS320C66x高性能DSP,

• Mission Critical
• Computing
• Communications
• Audio
• Video Infrastructure
• Imaging
• Analytics
• Networking
• Media Processing

Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

The 66AK2Hx platform is TI’s first to combine the quad ARM® Cortex™-A15 MPCore™ processors with up to eight TMS320C66x high-performance DSPs using the KeyStone II architecture. Unlike previous ARM Cortex-A15 devices that were designed for consumer products, the 66AK2Hx platform provides up to 5.6 GHz of ARM and 11.2 GHz of DSP processing coupled with security and packet processing and Ethernet switching, all at lower power than multi-chip solutions making it optimal for embedded infrastructure applications like cloud computing, media processing, high-performance computing, transcoding, security, gaming, analytics and virtual desktop. Using TI’s heterogeneous programming runtime software and tools, customers can easily develop differentiated products with 66AK2Hx SoCs.

The 66AK2Hx platform combines the quad ARMR Cortex™-A15 with up to eight TMS320C66x high-performance DSPs using the KeyStone II architecture. The 66AK2H14/12/06 provides up to 5.6 GHz of ARM and 9.6 GHz of DSP processing coupled with security, packet processing, and Ethernet switching at lower power than multi-chip solutions. It is optimal for embedded infrastructure applications like cloud computing, media processing, high-performance computing, transcoding, security, gaming, analytics, and virtual desktop.

The C66x core combines fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. It incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing.

The 66AK2H14/12/06 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.

The KeyStone II architecture provides many major enhancements over the previous KeyStone I generation of devices. The KeyStone II architecture integrates a Cortex-A15 processor quad-core cluster. The external memory bandwidth has been doubled with the integration of dual DDR3 1600 EMIFs. MSMC internal memory bandwidth is quadrupled with MSMC architecture improvements such as cache coherency. MSMC also enbles memories to operate at the speed of the processor cores, which reduces latency and contention while providing high-bandwidth interconnections between processor cores and shared internal and external memory. Multicore Navigator supports 2× the number of queues, descriptors, and packet DMA, 4× the number of micro RISC engines, and a significant increase in the number of push/pops per second compared to the previous generation. The new peripherals that have been added include the USB 3.0 controller, and asynchronous EMIF controller for NAND/NOR memory access.

The 3-port Gigabit Ethernet switch in KeyStone I has been replaced with a 5-port Gigabit Ethernet switch in KeyStone II. Time synchronization support has been enhanced to reduce software workload and support additional standards like IEEE1588 Annex D/E and SyncE. The number of GPIOs and serial interface peripherals, like I2C and SPI, have been increased to enable more board level control functionality.

66AK2H14/12/06主要特性:

• Eight (66AK2H14/12) or Four (66AK2H06) TMS320C66x™ DSP Core Subsystems (C66x CorePacs), Each With
– Up to 1.2 GHz C66x Fixed/Floating-Point DSP Cores
› 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
› 19.2 GFlops/Core for Floating Point @ 1.2 GHz
– Memory
› 32K Byte L1P Per CorePac
› 32K Byte L1D Per CorePac
› 1024K Byte Local L2 Per CorePac
• ARMR Cortex™-A15 MPCore™ Processors Containing Four (66AK2H14/12) or Two (66AK2H06) ARM Cortex-A15 Cores
– Up to 1.4-GHz Cortex-A15 Processor Core Speed
– 4MB L2 Cache Memory Shared by All ARM CorePacs
– Full Implementation of ARMv7-A Architecture Instruction Set
– 32KB L1 Instruction Cache and Data Cache per Cortex-A15 Processor Core
– AMBA 4.0 AXI Coherency Extension (ACE) Master Port, Connected to MSMC for Low Latency Access to Shared MSMC SRAM
• Multicore Shared Memory Controller (MSMC)
– 6 MB MSM SRAM Memory Shared by DSP CorePacs and ARM CorePac
– Memory Protection Unit for Both MSM SRAM and DDR3_EMIF
• Multicore Navigator
– 16k Multi-Purpose Hardware Queues with Queue Manager
– Packet-Based DMA for Zero-Overhead Transfers
• Network Coprocessor
– Packet Accelerator Enables Support for
› Transport Plane IPsec, GTP-U, SCTP, PDCP
› L2 User Plane PDCP (RoHC, Air Ciphering)
› 1 Gbps Wire Speed Throughput at 1.5 MPackets Per Second
– Security Accelerator Engine Enables Support for
› IPSec, SRTP, 3GPP and WiMAX Air Interface, and SSL/TLS Security
› ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit Hash), MD5
› Up To 2.4 Gbps IPSec and 2.4 Gbps Air Ciphering
– Ethernet Subsystem
› Five-Port Switch (four SGMII ports)
• Peripherals
– Four Lanes of SRIO 2.1
› Supports Up To 5 GBaud
› Supports Direct I/O, Message Passing
– Two Lanes PCIe Gen2
› Supports Up To 5 GBaud
– TwoHyperLink
› Supports Connections to Other KeyStone Architecture Devices Providing Resource Scalability
› Supports Up To 50 GBaud
– 10-Gigabit Ethernet (10-GbE) Switch Subsystem (66AK2H14 only)
› Two XFI Ports
› IEEE1588 Support
– Five Enhanced Direct Memory Access (EDMA) Modules
– Two 72-Bit DDR3 Interfaces with Speeds Up To 1600 MHz
– EMIF16 Interface
– USB 3.0
– Two UART Interfaces
– Three I2C Interfaces
– 32 GPIO Pins
– Three SPI Interfaces
– Semaphore Module
– 64-Bit Timers
› Twenty 64-Bit Timers for 66AK2H14/12
› Fourteen 64-Bit Timers for 66AK206
– Five On-Chip PLLs
• Commercial Case Temperature:
– 0℃ to 85℃
• Extended Case Temperature:
– - 40℃ to 100℃

66AK2H14/12/06应用:

• Mission Critical
• Computing
• Communications
• Audio
• Video Infrastructure
• Imaging
• Analytics
• Networking
• Media Processing


图1. 66AK2H14功能框图

66AK2H评估模块(EVM)

The 66AK2H Evaluation Module (EVM) is a fully featured, robust development tool for embedded high performance compute systems. It includes new hardware features and highly optimized software – for under $1,000. The EVM features a single 66AK2H14 System on Chip (SoC), an LCD display and an on-board emulation to help developers quickly start designing in 66AK2H14, 66AK2H12 or 66AKH06 SOCs that support multiple ARM A15 and C66x DSP cores. The EVM is enabled with two 10GB Ethernet interfaces for a bandwidth of 20Gbps backplane connectivity and optional wire rate switching in high density systems. A 10GB adaptor card (sold separately) is needed to optically connect to the EVM.

66AK2H EVM Image (Angle)

图2. 66AK2H评估模块(EVM)外形图

66AK2H评估模块(EVM)主要特性:

Computational performance is an industry-leading 28.4 GMACS/DSP core and 10.2 GFLOPS/DSP core (@1.2 GHz operating frequency), making K2H ideal for applications requiring significant signal processing, such as real-time military applications, medical imaging and geological exploration.

The software accompanying the 66AK2H EVM is TI’s Multicore Software Development Kit (MCSDK), enabling fast development through production ready foundational software. The MCSDK provides highly-optimized bundles of foundational, platform-specific drivers, optimized libraries and demos to enable development.

66AK2H评估模块(EVM)包括: 

66AK2H14 Evaluation Module
Power adapter and power cord
USB cable for on-board JTAG emulation (XDS200)
Mini-USB cable
Ethernet cable
RS-232 serial cable
Universal Plug Adapter
Documentation


图3.66AK2H评估模块(EVM)框图

图4.66AK2H评估模块(EVM)电路图(1)

图5.66AK2H评估模块(EVM)电路图(2)

图6.66AK2H评估模块(EVM)电路图(3)

图7.66AK2H评估模块(EVM)电路图(4)

图8.66AK2H评估模块(EVM)电路图(5)

图9.66AK2H评估模块(EVM)电路图(6)

图10.66AK2H评估模块(EVM)电路图(7)

图11.66AK2H评估模块(EVM)电路图(8)

图12.66AK2H评估模块(EVM)电路图(9)

图13.66AK2H评估模块(EVM)电路图(10)

图14.66AK2H评估模块(EVM)电路图(11)

图14.66AK2H评估模块(EVM)电路图(12)

图16.66AK2H评估模块(EVM)电路图(13)

图17.66AK2H评估模块(EVM)电路图(14)

图18.66AK2H评估模块(EVM)电路图(15)

图19.66AK2H评估模块(EVM)电路图(16)

图20.66AK2H评估模块(EVM)电路图(17)

图21.66AK2H评估模块(EVM)电路图(18)

图22.66AK2H评估模块(EVM)电路图(19)

图23.66AK2H评估模块(EVM)电路图(20)

图24.66AK2H评估模块(EVM)电路图(21)

图25.66AK2H评估模块(EVM)电路图(22)

图26.66AK2H评估模块(EVM)电路图(23)

图27.66AK2H评估模块(EVM)电路图(24)

图28.66AK2H评估模块(EVM)电路图(25)

图29.66AK2H评估模块(EVM)电路图(26)

图30.66AK2H评估模块(EVM)电路图(27)

图31.66AK2H评估模块(EVM)电路图(28)

图32.66AK2H评估模块(EVM)电路图(29)

图33.66AK2H评估模块(EVM)电路图(30)

图34.66AK2H评估模块(EVM)电路图(31)

图35.66AK2H评估模块(EVM)电路图(32)

图36.66AK2H评估模块(EVM)电路图(33)

图37.66AK2H评估模块(EVM)电路图(34)

图38.66AK2H评估模块(EVM)电路图(35)

图39.66AK2H评估模块(EVM)电路图(36)

图40.66AK2H评估模块(EVM)电路图(37)

图41.66AK2H评估模块(EVM)PCB布局图

66AK2H评估模块(EVM)材料清单见:
66AK2H评估模块(EVM)材料清单.rar

详情请见:
http://www.ti.com/lit/ds/symlink/66ak2h14.pdf
http://wfcache.advantech.com/www/support/TI-EVM/download/XTCIEVMK2X_Technical_Reference_Manual_Rev1_0.pdf
以及http://wfcache.advantech.com/www/support/TI-EVM/download/Schematics/PDF/K2H_K2EVM-HK_SCH_A102_Rev1_0.pdf

66ak2h14.pdf
K2H_K2EVM-HK_SCH_A102_Rev1_0.pdf
XTCIEVMK2X_Technical_Reference_Manual_Rev1_0.pdf
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