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  [组图]ADI ADP5053 Altera FPGA电源解决方案           ★★★ 【字体:
ADI ADP5053 Altera FPGA电源解决方案
作者:ADI    文章来源:ADI    点击数:    更新时间:2014-2-17    
ADI公司的ADP5053是四路高性能DC/DC降压转换器,并集成了监测电路,看门狗定时器和手动重置,输入电压4.5V-15.0V,全温度范围内的输出精度±1.5%,可调开关频率250kHz-1.4MHz,固定/可调输出,主要用在小型基站,FPGA和处理器电源,安全和监视,医疗电子.本文介绍了ADP5053主要特性,框图, 典型应用电路图以及多种Altera FPGA电源解决方案详细电路图和材料清单.

The ADP5053 combines four high performance buck regulators, a supervisory circuit, a watchdog timer, and a manual reset in a 48-lead LFCSP package that meets demanding performance and board space requirements. The device enables direct connection to high input voltages up to 15.0 V with no preregulators.

Channel 1 and Channel 2 integrate high-side power MOSFET and low-side MOSFET drivers. External NFETs can be used in low-side power devices to achieve an efficiency optimized solution and deliver a programmable output current of 1.2 A, 2.5 A, or 4 A. Combining Channel 1 and Channel 2 in a parallel configuration can provide a single output with up to 8 A of current.

Channel 3 and Channel 4 integrate both high-side and low-side MOSFETs to deliver an output current of 1.2 A.

The switching frequency of the ADP5053 can be programmed or synchronized to an external clock. The ADP5053 contains a precision enable pin on each channel for easy power-up sequencing or adjustable UVLO threshold.

The ADP5053 contains supervisory circuits that monitor the voltage level. The watchdog timer can generate a reset if the WDI pin is not toggled within a preset timeout period. Processor reset mode or system power on/off switch mode can be selected for manual reset functionality.

ADP5053主要特性:

Wide input voltage range: 4.5 V to 15.0 V
±1.5% output accuracy over full temperature range
250 kHz to 1.4 MHz adjustable switching frequency
Adjustable/fixed output options via factory fuse
Power regulation
Channel 1 and Channel 2: programmable 1.2 A/2.5 A/4 A sync buck regulators with low-side FET driver
Channel 3 and Channel 4: 1.2 A sync buck regulators
Single 8 A output (Channel 1 and Channel 2 operated in parallel)
Precision enable with 0.8 V accurate threshold
Active output discharge switch
FPWM or automatic PWM/PSM selection
Frequency synchronization input or output
Optional latch-off protection on OVP/OCP failure
Power-good flag on selected channels
UVLO, OCP, and TSD protection
Open-drain processor reset with external adjustable threshold monitoring
Watchdog refresh input
Manual reset input

ADP5053应用:

Small cell base stations
FPGA and processor applications
Security and surveillance
Medical applications


图1. ADP5053框图

图2. ADP5053典型应用电路图:开关频率600kHz,固定输出模式


图3. ADP5053典型应用电路图:开关频率600kHz,可调输出模式

图4. ADP5053典型应用电路图:开关频率600kHz,可调输出模式,通路1/通路2并联输出

Altera FPGA电源解决方案

Modern high performance FPGA-based systems require an increasing number of dedicated rails supplying core, I/O, memory, PLL, and precision analog voltages. Typical FPGA-based systems today make use of standalone switching regulators and LDOs; but, as board area continues to shrink as end product form factors shrink, this complicates the task of designing more efficient power management solutions for powering FPGAs. Combining multiple switching regulators and LDOs into a single package enables very small, flexible, highly efficient power management solutions for powering FPGAs and precision analog components with the highest system reliability.


图5.ADP5050 Altera FPGA电源解决方案框图

图6.ADP5050 Altera FPGA电源解决方案外形图

图7.ADP5050 Cyclone V (GX/SX) FPGA电源解决方案外形图

图8.ADP5050 Cyclone V FPGA电源解决方案框图
ADP5050 Cyclone V FPGA电源解决方案材料清单:


图9.ADP5050 Stratix IV FPGA电源解决方案框图
ADP5050 Stratix IV FPGA电源解决方案材料清单:


图10.ADP5050 Stratix V FPGA电源解决方案框图
ADP5050 Stratix V FPGA电源解决方案材料清单:


图11.ADP5050 Arria V FPGA电源解决方案框图
ADP5050 Arria V FPGA电源解决方案材料清单:

详情请见:
http://www.analog.com/static/imported-files/data_sheets/ADP5053.pdf
http://www.analog.com/static/imported-files/pwr_mgmt/fs_pod_collateral/Integrated-Power-Solutions-for-Altera-FPGAs.pdf

ADP5053.pdf
Integrated-Power-Solutions-for-Altera-FPGAs.pdf
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